Tanmay's Log
Tanmay Bhola (Talk | contribs) |
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Log of My Research and Design for the COSC 427 Design Study | Log of My Research and Design for the COSC 427 Design Study | ||
| − | == 19th | + | === 19th July === |
-- Referring to the Book "Structure and Interpretation of Computer Programs" 2nd Edition, by Harold Abelson, Gerald Jay Sussman (1996) . | -- Referring to the Book "Structure and Interpretation of Computer Programs" 2nd Edition, by Harold Abelson, Gerald Jay Sussman (1996) . | ||
| Line 16: | Line 16: | ||
(2 Hours) | (2 Hours) | ||
| + | |||
| + | === 25th July === | ||
| + | [2 Hours] | ||
| + | Read further about Simulators, Digital Logic Blocks | ||
| + | |||
| + | ===26th July === | ||
| + | [3 Hours] | ||
| + | Read up about Test Driven Development, JUnit and Software Refactoring from the Library books on these topics | ||
| + | |||
| + | === 1 August === | ||
| + | [5 hours] | ||
| + | Updated the Design Study page. Finally added some small circuit and block diagram on the page. | ||
| + | Thought about Modelling Components and Wires. | ||
---- | ---- | ||
Revision as of 11:45, 1 August 2010
Log of My Research and Design for the COSC 427 Design Study
Contents |
19th July
-- Referring to the Book "Structure and Interpretation of Computer Programs" 2nd Edition, by Harold Abelson, Gerald Jay Sussman (1996) .
Event Driven Simulation: In which Actions (Events) trigger further events that happen at a later point in time, which trigger further events and so on.
Objects to be modeled: -- Real Life elementary components:
- 1) Wires --- Carry binary signals : 0 / 1. They also have to perform some tasks (inform connected components) about change in their value.
- 2) Digital Function Blocks --- Which are connected between Wires carrying inputs to other wires - outputs. These need to listen for changes in the state of wires connecting these blocks. A change in the state of 1 wire might trickle down to changes in the neighboring wires based on the output of these function blocks.
- 3) Operations Queue --- to help model the time delay of performing various tasks during the simulation.
- 4) Probe --- To trigger on change in value and print value on screen
(2 Hours)
25th July
[2 Hours] Read further about Simulators, Digital Logic Blocks
26th July
[3 Hours] Read up about Test Driven Development, JUnit and Software Refactoring from the Library books on these topics
1 August
[5 hours] Updated the Design Study page. Finally added some small circuit and block diagram on the page. Thought about Modelling Components and Wires.
