Tanmay's Design Study

Revision as of 03:23, 1 August 2010

Introduction

Welcome to the world of Digital Logic. Ever wondered what they teach at the College of Engineering that is different from the material taught at Department of Computer Science and Software Engineering ? Being a computer engineering student, I thought I would take this opportunity to perform Object-Oriented Analysis and Design of a 'Digital Logic Circuit Simulator'.Digital Circuits, that are constructed by joining simple logic elements, form the basis of our 'Embedded Systems' oriented programme.

Outline

A digital logic simulator gives the user the ability to join simple logic elements to study the behaviour of complex digital circuits. My approach to this problem would be designing an 'Event Driven Simulator' where events (change in state of something) triggers further events in the system that happen at a later time. This model of this simulator will revolve around the elementary components from which the circuit is constructed as well as the time-events taking place in the system. These can be further broken down into :

1) Wires --- Carry binary signals : 0 / 1. They also have to perform some tasks (inform connected components) about change in their value.

2) Digital Function Blocks --- Which are connected between Wires carrying inputs to other wires - outputs. These need to listen for changes in the state of wires connecting these blocks. A change in the state of 1 wire might trickle down to changes in the neighboring wires based on the output of these function blocks.

3) Events --- to help model the time delay of performing various tasks during the simulation.

Background

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  Logic Gates

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  Half Adder Circuit

User Stories

Class Description

Initial Design